A Syn thesis Preprocessor that Converts Implicit St yle V erilog Into One-Hot Designs

Di erent synthesis vendors support di erent subsets of Verilog. One such subset is the implicit style state machine (multiple uses of edge triggered events within an always block). With this style, one c an obtain working silicon in less time because the implicit style is more like software design. Unfortunately, most synthesis vendors do not support the implicit style. To make the implicit style more accessible, a freely available synthesis preprocessor is described here that converts implicit style always blocks into other equivalent Verilog, which can then be synthesized by most commercial synthesis tools. This paper discusses advantages of the implicit style, how the preprocessor translates implicit style code into a one-hot design, and why the language subset (non-blocking assignment) was chosen so that the semantics of the synthesized Verilog can agree with the simulation semantics de ned by IEEE 1364. More information about our preprocessor can be found at http://plum.uwyo.edu/~vito or http://cs.brockport.edu/~jshuler/vito/.